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ly651024 rev. 1.1 128k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 0 ? revision history revision description issue date rev. 1.0 initial issue a ug.27.2010 rev. 1.1 delete e-grade apr. 06. 2012
ly651024 rev. 1.1 128k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 1 ? features ? fast access time : 20ns ? low power consumption: operating current : 30ma (typ.) standby current : 2 a (typ.) ? single 5v power supply ? all inputs and outputs ttl compatible ? fully static operation ? tri-state output ? data retention voltage : 2.0v (min.) ? green package available ? package : 32-pin 300 mil soj 32-pin 8mm x 20mm tsop-i 32-pin 8mm x 13.4mm stsop general description the ly651024 is a 1,048,576-bit low power cmos static random access memory organized as 131,072 words by 8 bits. it is fabricated using very high performance, high reliability cmos technology. its standby current is stable within the range of operating temperature. the ly651024 is well designed for very high speed system applications, and particularly well suited for battery back-up nonvolatile memory application. the ly651024 operates from a single power supply of 3v~5v and all inputs and outputs are fully ttl compatible product family product family operating temperature vcc range speed power dissipation standby(i sb1, typ.) operating(icc,typ.) ly651024(ll) 0 ~ 70 4.5 ~ 5.5v 20ns 2a 30ma ly651024(lli) -40 ~ 85 4.5 ~ 5.5v 20ns 2a 30ma functional block diagram decoder i/o data circuit control circuit 128kx8 memory array column i/o a0-a16 vcc vss dq0-dq7 ce# we# oe# ce2 pin description symbol description a0 - a16 address inputs dq0 ? dq7 data inputs/outputs ce#, ce2 chip enable inputs we# write enable input oe# output enable input v cc power supply v ss ground nc no connection pin configuration
ly651024 rev. 1.1 128k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 2 ? a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 vss a14 vcc a8 a9 a11 a10 dq7 dq6 dq5 dq4 dq3 ly651024 soj 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 16 15 20 19 18 22 23 24 25 26 27 21 a13 ce# oe# we# a16 nc 29 32 30 31 ce2 a15 tsop-i/stsop dq3 a11 a9 a8 a13 dq2 a10 a14 a12 a7 a6 a5 vcc dq7 dq6 dq5 dq4 vss dq1 dq0 a0 a1 a2 a4 a3 ly651024 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 16 15 20 19 18 22 23 24 25 26 27 21 oe# we# ce# ce2 a15 a16 nc 32 31 29 30 absolute maximun ratings* parameter symbol rating unit voltage on v cc relative to v ss v t1 -0.5 to 6.5 v voltage on any other pin relative to v ss v t2 -0.5 to v cc +0.5 v operating temperature t a 0 to 70(c grade) -40 to 85(i grade) storage temperature t stg -65 to 150 power dissipation p d 1 w dc output current i out 50 ma *stresses greater than those listed under ?absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only and functional operation of the device or any other conditions above t hose indicated in the operati onal sections of this s pecification is not implied. exposure to the absolute ma ximum rating conditions for extended per iod may affect device reliability. truth table mode ce# ce2 oe# we# i/o operation supply current standby h x x x high-z i sb ,i sb1 x l x x high-z i sb ,i sb1 output disable l h h h high-z i cc read l h l h d out i cc write l h x l d in i cc note: h = v ih , l = v il , x = don't care.
ly651024 rev. 1.1 128k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 3 ? dc electrical characteristics parameter symbol test condition min. typ. * 4 max. unit supply voltage v cc 4.5 5.0 5.5 v input high voltage v ih *1 2.4 - v cc +0.5 v input low voltage v il *2 - 0.5 - 0.8 v input leakage current i li v cc R v in R v ss - 1 - 1 a output leakage current i lo v cc R v out R v ss, output disabled - 1 - 1 a output high voltage v oh i oh = -4m a 2.4 - - v output low voltage v ol i ol = 8m a - - 0.4 v average operating power supply current i cc cycle time = min. ce# = v il and ce2 = v ih , i i/o = 0ma, others at v il or v ih - 30 55 ma standby power supply current i sb ce# = v ih or ce2 = v il others at v il or v ih - 1 5 ma i sb1 ce# v R cc -0.2v or ce2 Q 0.2v others at 0.2v or v cc -0.2v - 2 50 a notes: 1. v ih (max) = v cc + 3.0v for pulse width less than 10ns. 2. v il (min) = v ss - 3.0v for pulse width less than 10ns. 3. over/undershoot specifications are characterized, not 100% tested. 4. typical values are included for reference only and are not guaranteed or tested. typical valued are measured at v cc = v cc (typ.) and t a = 25 capacitance (t a = 25 , f = 1.0mhz) parameter symbol min. ma x unit input capacitance c in - 6 pf input/output capacitance c i/o - 8 pf note : these parameters are guaranteed by devic e characterization, but not production tested. ac test conditions input pulse levels 0.2v to v cc -0.2v input rise and fall times 3ns input and output timing reference levels 1.5v output load c l = 30pf + 1ttl, i oh / i ol = -4ma/8m a
ly651024 rev. 1.1 128k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 4 ? ac electrical characteristics (1) read cycle parameter sym. ly651024-20 unit min. ma x . read cycle time t rc 20 - ns a ddress access time t aa -20ns chip enable access time t ace -20ns output enable access time t oe -8ns chip enable to output in low-z t clz * 4 - ns output enable to output in low-z t olz * 0 - ns chip disable to output in high-z t chz *-8ns output disable to output in high-z t ohz *-8ns output hold from address change t oh 3-ns (2) write cycle parameter sym. ly651024-20 unit min. max. write cycle time t wc 20 - ns a ddress valid to end of write t aw 16 - ns chip enable to end of write t cw 16 - ns a ddress set-up time t as 0-ns write pulse width t wp 11 - ns write recovery time t wr 0-ns data to write time overlap t dw 9-ns data hold from end of write time t dh 0-ns output active from end of write t ow * 5 - ns write to output in high-z t whz * - 9 ns *these parameters are guaranteed by device characterization, but not production tested.
ly651024 rev. 1.1 128k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 5 ? timing waveforms read cycle 1 (address controlled) (1,2) dout data valid t oh t aa address t rc previous data valid read cycle 2 (ce# and ce2 and oe# controlled) (1,3,4,5) dout data valid t oh oe# high-z high-z t clz t olz t oe t chz t ohz ce2 t ace ce# t aa address t rc notes : 1.we# is high for read cycle. 2.device is continuously selected oe# = low, ce# = low ., ce2 = high . 3.address must be valid prior to or coincident with ce# = low , ce2 = high; otherwise t aa is the limiting parameter. 4.t clz , t olz , t chz and t ohz are specified with c l = 5pf. transition is measured 500mv from steady state. 5.at any given temperature and voltage condition, t chz is less than t clz , t ohz is less than t olz.
ly651024 rev. 1.1 128k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 6 ? write cycle 1 (we# controlled) (1,2,3,5,6) dout din data valid t dw t dh (4) high-z t whz we# t wp t cw t wr t as (4) t ow ce# t aw address t wc ce2 write cycle 2 (ce# and ce2 controlled) (1,2,5,6) dout din data valid t dw t dh (4) high-z t whz we# t wp t cw ce# t wr t as t aw address t wc ce2 notes : 1.we#, ce# must be high or ce2 must be low during all address transitions. 2.a write occurs during the overlap of a low ce#, high ce2, low we#. 3.during a we#controlled write cycle with oe# low, t wp must be greater than t whz + t dw to allow the drivers to turn off and data to be placed on the bus. 4.during this period, i/o pins are in the out put state, and input signals must not be applied. 5.if the ce#low transition and ce2 high transit ion occurs simultaneously with or after we# low transition, the outputs remain i n a high impedance state. 6.t ow and t whz are specified with c l = 5pf. transition is measured 500mv from steady state.
ly651024 rev. 1.1 128k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 7 ? data retention characteristics parameter symbol test condition min. typ. max. unit v cc for data retention v dr ce# v R cc -0.2vor ce2 Q 0.2v 2.0 - 5.5 v data retention current i dr v cc = 2.0v ce# v R cc - 0.2v or ce2 Q 0.2v others at 0.2v or v cc -0.2v - 0.5 30 a chip disable to data retention time t cdr see data retention waveforms (below) 0 - - ns recovery time t r t rc * - - ns t rc * = read cycle time data retention waveform low vcc data retention waveform (1) ( ce# controlled) vcc ce# v dr R 2.0v ce# v R cc-0.2v vcc(min.) v ih t r t cdr v ih vcc(min.) low vcc data retention waveform (2) (ce2 controlled) vcc ce2 v dr R 2.0v ce2 Q 0.2v vcc(min.) v il t r t cdr v il vcc(min.)
ly651024 rev. 1.1 128k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 8 ? package outline dimension 32 pin 300mil soj package outline dimension unit symbol inch(base) mm(ref) a 0.148(m a x) 3.759(m a x) a 1 0.025(min) 0.635(min) a 2 0.123(m a x) 3.124(m a x) b 0.018(typ) 0.457(typ) d 0.825 0.005 20.955 0.127 e 0.335(typ) 8.509(typ) e1 0.300 0.005 7.620 0.127 e 0.050(typ) 1.270(typ) l 0.086 0.010 2.184 0.254 y 0.003(max) 0.076(m a x) 32 pin 8mm x 20mm tsop-i package outline dimension
ly651024 rev. 1.1 128k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 9 ? unit sym. inch(base) mm(ref) a 0.047 (max) 1.20 (max) a1 0.004 0.002 0.10 0.05 a2 0.039 0.002 1.00 0.05 b 0.009 0.002 0.22 0.05 c 0.006 0.002 0.155 0.055 d 0.724 0.008 18.40 0.20 e 0.315 0.008 8.00 0.20 e 0.020 (typ) 0.50 (typ) hd 0.787 0.008 20.00 0.20 l 0.024 0.004 0.60 0.10 l1 0.0315 0.004 0.08 0.10 y 0.003 (max) 0.08 (max) 0 o 5 o 0 o 5 o
ly651024 rev. 1.1 128k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 10 ? 32 pin 8mm x 13.4mm stsop package outline dimension unit sym. inch(base) mm(ref) a 0.049 (max) 1.25 (max) a1 0.004 0.002 0.10 0.05 a2 0.039 0.002 1.00 0.05 b 0.009 0.002 0.22 0.05 c 0.006 0.002 0.155 0.055 d 0.465 0.008 11.80 0.20 e 0.315 0.008 8.00 0.20 e 0.020 (typ) 0.50 (typ) hd 0.528 0.008 13.40 0.20. l 0.02 0.008 0.50 0.20 l1 0.031 0.005 0.8 0.125 y 0.003 (max) 0.076 (max) 0 o 5 o 0 o 5 o
ly651024 rev. 1.1 128k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 11 ? ordering information
ly651024 rev. 1.1 128k x 8 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 12 ? this page is left blank intentionally.

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